Senior Verification Engineer
Job Code: AL_VE_USA_01
- Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an added
- Expertise in SystemVerilog, System C,Verification Methodologies such as OVM,UVM,etc.
- Should have worked on at least one full-chip or module-level verification using HVLs.
- Experience in developing verification plans, Verification environments, Components/BFMs and running
simulations at RTL and gate level.
- Knowledge of C/C++ would be an added advantage.
- Possess excellent debugging and problem solving skills.
- Excellent written and verbal communication skills.
- Should be willing to work as an Individual contributor or team environment.