Overview
The Atria Logic AL-H264D-REFD is a compact and low power, embedded AVC (H.264) streaming video decoder reference design, targeted for industrial and CE applications. Industrial applications include remote monitoring of manufacturing plants and digital signage for advertising and information displays in hotels, ATMs, gas pumps, kiosks, etc. CE applications include in-flight and automotive infotainment systems.
The reference design uses a complete set of Atria Logic's IP blocks in an Altera Cyclone-III FPGA. The design includes a hardware implementation of an AVC Baseline Profile decoder, a 10/100Base-T Ethernet MAC and PHY for TS-over-IP input to the decoder, a Flash controller and reader for file-based input to the decoder and an LCD display controller for output of the decoded video to an LCD display. An integrated multi-port DDR controller supports external DDR, and an integrated UART/USB controller supports an external host interface for configuration and control.
The high level of integration results in a very compact and low power footprint. All the Atria Logic IP blocks used in the reference design are easily targeted to other FPGAs and to SoCs. Alternatively, the decoder can also be fully implemented in software on an Altera NIOS or ARM Cortex-M1 embedded processor. The implementation on an Altera Cyclone-III FPGA or on an Altera NIOS or ARM Cortex-M1 embedded processor addresses low power and cost-sensitive requirements.
Block Diagram
Applications
- Remote monitoring
- Digital signage
- In-flight infotainment
- Automotive infotainment
Features
- H.264 Baseline Profile up to Level 4.2 video decode
- Low power, low gate count (30fps CIF decode at 12 MHz)
- Atria Logic H.264 decoder, multi-port DDR1/2 controller, USB2.0 Device/UART controller, 10/100 Ethernet MAC, LCD and Flash controller IP blocks
- On-chip AMBA AXI/AXI-Lite or Altera Avalon interconnect fabric
- Single 50MHz clock input
- On-chip clock gating and software controlled clocks and resets
- Altera Cyclone III FPGA implementation
Benefits
- Easily portable to SW-only or mixed SW/HW to ARM Cortex-M1 or Altera NIOS processors
- Easily portable to SoC designs
- Scalable to multiple video streams at higher clock rates
- Low power implementation
- Low gate count implementation
- Cost-sensitive implementation