Memory Controller IP

High speed QDR IV Extreme Performance (XP) PHY and memory controller with 800MHz memory interface and 200MHz user interface, for next generation high-performance memories.

Reusable, user-friendly, configurable verification component IP in SystemVerilog at the IP or system level, for FPGA and SoC implementations. 

Fully configurable to JEDEC specifications, with efficient and pipelined interface to DDR-I and DDR-II SDRAM devices for FPGA and SoC implementations.