Atria Logic Hybrid Memory Cube verification IP is a reusable, configurable verification component developed using SystemVerilog. The IP offers an easy-to-use and complete verification solution for SoC's using the HMC Host Controller at the IP level or system-level. The HMC VIP consists of two components:
The Device Model listens on the HMC interface (128-bit) for packets/flits and responds to requests from the Host. The device model VIP is designed to be comply with the HMC Specification v 1.0 and supports all the transaction types mentioned in the specification.
The HMC Analyzer snoops both the TX and RX interfaces of the HMC Device/Host and captures all the packets/flits sent on the bus. It checks the links for compliance with the HMC specification, for example, Link retry, writes and reads. The Analyzer also includes coverage statistics to monitor the number and type of transactions on the HMC interface.
Both these components can be used in tandem or as stand-alone components in the Verification Environment.
The HMC Verification IP is developed using a layered architecture as shown in the following figure. This allows both the modules to be highly configurable, coverage driven, and also allows for constrained random generation.
The HMC VIP can be used to verify any HMC Host Controller which is compliant with the HMC Specification v1.0. The VIP can be used in the functional verification of IPs, SoC designs that incorporate the Hybrid Memory Cube Host Controllers.
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