Atria Logic with its vast expertise and working experience for more than a decade in memory domains, brings a high speed PHY and Memory Controller for next generation memories introduced under the QDR consortium. Working at high speeds it garnishes the maximum speed of Stratix V FPGAs at 800MHz. De- skew training sequences, per-bit calibration and rate conversions at high speeds from uer interface (quarter rate) to memory interface (full rate) are some its features.

Key Features

  • Two-Bidirectional Ports
  • De-skew training sequence
  • Reset configuration and calibration sequences at hard-reset
  • On-die termination
  • Work upto 800MHz

Block Diagram


  • FPGA specific netlist
  • Complete HDLtestbench
  • Test images
  • Data Sheet and Users Guide

Licensing Options

  • Evaluation
  • Project
  • Unlimited

QDR4 PHY Features:

feature Description
FPGA family Stratix V
Maximum Frequency 800MHz
Data width supported X18 : 2 ports port A, port B
Burst Length 2
Address DDR, Rising edge : port A; Falling edge : port B
Commands Separate command ports for port A and port B SDR
Clocks, Strobes Differential Clocks :
CK/CK# : Address,commands
DK/DK# : Write Data
QK/QK#(from memory) : Read Data
Write Latency at Memory Interface 5 Clock cycles
Read Latency at Memory Interface 8 Clock cycles
User Interface (Frequency) Quarter Rate
Memory Interface (Frequency) Full Rate
Calibration (with per-bit deskew support) Supported for Address, command, write and read data paths through firmware
Coarse and Fine Delay control On Address, Command, Write and Read path
Datapath on memory interface 2 separate data ports for port A and port B. Bidirectional and DDR. 72b data transaction at one full rate cycle
Read and Write data strobes Free running clock strobes for write and read data path.
Configuration on Memory during Reset Supported
MSR Writes/Reads Supported
ODT termination ports for Data path Supported
Loopback Mode Supported


  • Standard: QDR IV XP (Extreme Performance) PHY and Memory Controller
  • Frequency: Memory Interface : 800MHz
  • User Interface : 200MHz
  • Write Latency at Memory Interface : 5 Full Rate Cycles
  • Read Latency at Memory Interface : 8 Full Rate Cycles
  • Burst Length : 2 Words
  • Calibration : Per-bit calibration for data, command and address on memory interface.
  • Data Modes: x18 mode supported at 2 ports respectively. At one FR cycle 2 x (18+18) = 72b of data transferred.
  • FPGA Platform: Stratix V FPGA


  • High performance networking and communication applications
  • Servers