SoC/ASIC/FPGA Services


Atria Logic offers design, development and testing services at various stages of electronic product development. Through our high quality service and commitment we help our clients to reduce time to market, development risk and project cost.

Our teams have vast experience in SoC/ASIC/FPGA design and verification and deep domain knowledge in the areas of video/image processing, high speed bus architectures, high speed memory controllers/interfaces and heterogeneous computing. Our teams have experience working with front-end tools from the major EDA companies like Cadence, Mentor Graphics and Synopsys, and experience designing with FPGA devices from Xilinx, Altera and Microsemi.

Our domain expertise includes, but is not limited to, medical imaging, multimedia, storage, networking, FPGA/SoC and embedded software design and verification. Our broad portfolio of high-performance IP cores and verification suites drastically reduces time to market of complex designs. With Atria Logic you are in good hands when farming out execution of your product development, regardless of complexity.

Our Service Offerings:

  • FPGA Design and Verification
  • ASIC RTL Design and Verification
  • Pre-Silicon and Post-Silicon Validation on FPGA
  • Design IP Development, Customization and Integration
  • Verification IP Development, Customization and Integration
  • New Product development based on FPGA
  • End to end FPGA implementations (Concept to System)
  • Complex projects with SoC architecture (Nios,Microblaze,ARM cores, Zynq devices)
  • In-depth exposure to major FPGA families Xilinx,Altera,Microsemi
  • ASIC Prototyping with FPGAs (Multi-FPGA implementations, Board design)
  • Rapid IP prototyping with FPGAs
  • Concept proving, Algorithm development for emerging technologies
  • Co-Processing applications development, implementations
  • Retargetting: FPGA-to-FPGA, FPGA-to-ASIC, ASIC-to-FPGA, Embedded system-to-FPGA
  • Feature addition, Enhancement, Upgradation of existing Designs
  • Micro-architecture Design
  • RTL Design & IP Development
  • SoC Integration
  • Functional Verification
  • Formal Verification
  • Design For Test (BIST, JTAG, SCAN, ATPG)
  • FPGA Prototyping on Xilinx, Altera, Actel Platforms
  • ASIC Physical Design 
  • (Synthesis, Floorplan, SDC Generation and Static Timing Analysis)
  • Gate ECO and Validation
  • ATE Vector Generation and Debug
  • Chip Bringup and System Debug


  • Methodologies - UVM, OVM, VMM
  • Tools Chains - Cadence, Mentor Graphics, Synopsys
  • FPGA Platforms - Xilinx, Altera, Microsemi
  • Prototyping Platforms - ARM-Development, Xilinx/Altera EVMs
  • Protocols - USB 3.0, HDMI, SerDes, PCIe, NVMe, DDR3/4, 1G/10G Ethernet