I2C is a two-wire, bidirectional serial bus that provides simple and efficient data transfer between devices. It uses serial data line (SDA) and serial clock line (SCL) for data transfers
The Controller core interfacing to I2C bus can be easily integrated to an embedded system via AHB, APB, Avalon bus fabrics or custom logic via simple register programming. The system can request the controller to perform I2C data transfers and also poll status. The core serializes system transmit data of 8, 16, 32 or 64 bytes on the SDA IO pin. It also de-serializes system receive data
In the master mode, the system can initiate write or read data transfer to the slave by programming the memory mapped registers within the Controller core. Byte transfers can be single or bursts (programmable size) based on the control writes to registers.
The IP core is implemented in Altera Cyclone-III and Xilinx Virtex 4 FPGA devices. Device utilization details are:
The IP core is implemented in Altera Cyclone-III and Xilinx Virtex 4 FPGA devices. Device utilization details are:
DEVICE | AREA | PERFORMANCE |
---|---|---|
ALTERA CYCLONE III | 700 LC | Fmax = 100 MHz |
XILINX VIRTEX 4 | 360 LC | Fmax = 100 MHz |
Copyright © 2015-16 Atria Logic Inc.