The AL_EMAC_CORE Ethernet MAC Core is hardware implementation of Ethernet protocol defined by IEEE 802.3-2005 Specification. This core transmits and receives Ethernet frames to and from Ethernet network in all three speeds 10/100/1000 Mbps. Both half-duplex and fullduplex mode of operation are supported at all three speeds. The core interfaces to an industry standard external PHY device through RGMII or GMII for Gigabit Ethernet and RGMII or MII for fast Ethernet.
This core is implemented in both Altera Cyclone-III and Xilinx Virtex-4 FPGA. This core also supports pause frame control based on user programmable register setting.
The IP core is implemented in Altera Cyclone-III and Xilinx Virtex 4 FPGA devices. Device utilization details are:
|ALTERA CYCLONE III||2000 LC||Fmax = 125 MHz|
|XILINX VIRTEX 4||900 LC||Fmax = 125 MHz|
Copyright © 2015-16 Atria Logic Inc.