Standard Bus Architecture IP

PCI-SIG's PCIe v2.0 specification compliant PHY core with configurable PIPE interface (8/16 bit/ 32bit) and highly efficient architecture with minimal gate count. Supports generation of whole range of Ordered Sets as required by PCIe 2.0 Specification with synchronized LTSSM and also includes IBM implementation compatible 8b/10b Encoder and Decoder.

High/full-speed (480Mbps/12Mbps), fully synthesizable, peripheral controller core with UTMI USB port transceiver and host microprocessor interfaces, user-configurable for up to 15 IN and OUT endpoints, and with power management and remote wake-up functions.

IEEE 802.3-2005 compliant, 10/100/1000Mbps Rx/Tx in half-duplex and full-duplex modes, Gigabit RGMII/GMII and fast Ethernet RGMII/MII support for interfacing to industry standard external PHY devices.

Two-wire, bidirectional I2C controller IP core with serial data (SDA) and serial clock (SCL) lines, readily integrated through simple register programming with AHB, APB and Avalon bus fabrics or custom logic.

UHN_IOL standards compliance and interoperability post silicon test suite for system level validation of NVMe controllers, with additionally test features for greater design and performance confidence, and support for Linux based environments and portability across systems.